Semiconductor storage device

ABSTRACT

An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode.  
     The transition from the deep stand-by mode to the stand-by mode starts first and second timer circuits  12  and  14  which respectively output a timer output TN of a constant cycle needed for self-refresh and a timing signal TR of a shorter cycle than a self-refresh cycle. A counter circuit  15  counts the output TR from the second timer circuit  14  immediately after the deep stand-by mode has been transitioned to the stand-by mode. If the counted value corresponds to a value as set, then the counter circuit  15  outputs an operation mode switching signal C. A selector circuit  17  comprising a multiplexer is switched and controlled by the output from the counter circuit  15 . The selector circuit  17  remains selecting TR until the counted value of the counter circuit  15  corresponds to the set value, and in the subsequent stand-by mode, the selector circuit  17  selects and outputs TN.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device, and moreparticularly to an operation control circuit of a semiconductor memorydevice having a plurality of operation modes.

BACKGROUND ART

Typical examples of random access semiconductor memory devices are SRAMand DRAM. SRAM is faster in read and write operations than DRAM. SRAM isfree of any refresh operations which are needed by DRAM. SRAM is thusmore convenient in operations and smaller in data holding current instand-by state. In contrast, each memory cell of SRAM needs sixtransistors. SRAM is larger in chip size and more expensive than DRAM.

Each memory cell of DRAM comprises a single capacitor and a singletransistor. DRAM has a larger memory capacity at a smaller chip sizethan SRAM. DRAM is lower in cost than SRAM, provided that both have thesame memory capacity. It is, however, necessary for DRAM that column androw addresses are given to DRAM separately from each other, providedthat DRAM takes the column address at a timing defined by RAS (a rowaddress strobe signal), and also takes the row address at another timingdefined by CAS (a column address strobe signal). DRAM, therefore, needsRAS and CAS as well as needs a control circuit for cyclical refreshoperations to memory cells. DRAM is more complicated in timing controland larger in comsumption of current than SRAM.

The majority of the semiconductor memory devices used in portableelectronic devices typically portable telephones is SRAM for thefollowing reasons. SRAM is smaller in stand-by current and lower incomsumption of power, for which reason SRAM is suitable for a portabletelephone device which needs improvements in a long continuouscommunication time and in a long continuous stand-by time.Notwithstanding, the conventional portable telephone device had a simplefunction and does not need a semiconductor memory device with a largecapacity. SRAM is easy in the timing control.

Meanwhile, the latest portable telephone device has an additionalfunction of transmission and receipt of e-mails and a still additionalfunction of both making an access to a WEB server on the Internet andsubsequently displaying simplified contents of home pages. It ispresumable that, similarly to the present personal computers, a futureportable telephone device is capable of making a free access to homepages on the Internet. In order to realize such the above-describedadditional functions, a graphic display is essential for serving avariety of multimedia informations to user, and also a semiconductormemory device with a large capacity is needed for temporary storing, inthe portable telephone device, a large amount of data received throughpublic networks.

On the other hand, the portable telephone device needs a small size, alight weight and a low power consumption, for which reason thesemiconductor memory device has an increased capacity, while it isdesired to avoid increases in size, weight and power comsumption of thesemiconductor memory device. As the semiconductor memory deviceintegrated in the portable telephone device, DRAM is preferable in viewof a large capacity, while SRAM is preferable in another view ofoperability and power comsumption. Such a semiconductor memory device ashaving both advantages of SRAM and DRAM seems optimum for the portableelectronic devices.

As such the above-described semiconductor memory device, a “pseudo-SRAM”has been proposed, which uses the same memory cells as DRAM and have thesame specifications and the same operations as SRAM in view of userside. The pseudo-SRAM is disclosed in Japanese laid-open patentpublications Nos. 61-5495, 62-188096, 63-206994, 4-243087 and 6-36557.

Since the pseudo-SRAM has the same memory cell structure as DRAM, it isnecessary for the pseudo-SRAM to perform cyclically refresh operationsfor holding data stored in memory cells thereof. The pseudo-SRAM is freeof such a stand-by mode as of the conventional SRAM, even thepseudo-SRAM is similar in operations to the SRAM. It is preferable thatthe pseudo-SRAM has such a low power consumption mode as thegeneral-purpose SRAM in view of operability as long as the pseudo-SRAMis operated in the same specification as the conventional SRAM.

The present inventions proposed, in view of the above-perspective, asemiconductor memory device which has a unique low power consumptionmode different from the existent semiconductor memory device, and whichhas a stand-by mode equivalent to the stand-by mode of thegeneral-purpose SRAM, with reference to the semiconductor device usingthe pseudo-SRAM, wherein the semiconductor memory device is disclosed inJapanese patent application No. 2000-363664 (Japanese laid-open patentpublication No. 2002-74944 and International Publication No.WO01/41149A1. In accordance with this conventional invention, twodifferent operation modes are set. The first operation mode is astand-by mode as the same power supply mode as in the normal DRAM forsupplying a power to circuits necessary for refresh of memory cells inorder to ensure data hold of the memory cells. The second operation modeis a deep stand-by mode which discontinues any power supply to thecircuits necessary for the refresh of the memory cells, thereby notensuring the data hold of the memory cells.

In this deep stand-by mode, it is impossible to hold the data of thememory cells, but any refresh operation is unnecessary. This reduces theconsumption of current in the deep stand-by mode as compared to thestand-by mode. This deep stand-by mode is available as long as allmemory cells of the memory cell array become allowed for writeoperations during a transition from the stand-by state into the activestate. This deep stand-by mode is suitable for using the semiconductormemory device as a buffer.

FIG. 1 is a block diagram illustrative of one example of theconfiguration of the essential part of the conventional pseudo SRAM. InFIG. 1, a voltage level control circuit 1 generates an internal voltagelevel control signal “A” based on first and second reference voltagesVref1 and Vref2. This internal voltage level control signal “A” is asignal for controlling a level of a boost voltage Vbt to be applied toword lines of a memory cell array 2. The internal voltage level controlsignal “A” is outputted from the voltage level control circuit 1 andthen inputted into a ring oscillator 3. The ring oscillator 3 isactivated and oscillated by “H” (high level) of the internal voltagelevel control signal “A” from the voltage level control circuit 1,whereby the ring oscillator 3 outputs an oscillation output “B”. Theoscillation output “B” outputted from the ring oscillator 3 is theninputted into a boost circuit 4.

The boost circuit 4 comprises a charge pump circuit for generating theboost voltage Vbt as an internal voltage. The boost circuit 4 boostsstep-by-step a power voltage VDD by utilizing the oscillation output “B”outputted from the ring oscillator 3 for generating the boost voltageVbt. This boost voltage Vbt is then inputted into a word decoder 5 fordriving a word line. The boost voltage Vbt is set at a level which ishigher than the power voltage VDD, for example, about VDD+1.5V toVDD+2V. The word decoder 5 supplies the boost voltage Vbt to a word lineselected by an output from a row decoder 6. The memory cell array 2comprises the same configuration as the memory cell array of DRAM.

A refresh timing generation circuit 7 generates a refresh signal and arefresh address, wherein the refresh signal is to refresh memory cellsin the memory cell array 2 at a constant time interval, while therefresh address is to designate an address of a memory cell which shouldbe refreshed. The refresh signal is outputted from the refresh timinggeneration circuit 7 and then inputted into a row enable generationcircuit 8. The refresh address is outputted from the refresh timinggeneration circuit 7 and then inputted into the row decoder 6. The rowenable generation circuit 8 generates a row enable signal LT at a timingwhen the refresh timing generation circuit 7 generates the refreshsignal.

The row enable generating circuit 8 receives inputs of a write enablesignal WE, a chip select signal CS and a read/write address Add of thememory cell array 2, and outputs the row enable signal LT every time theread/write address Add is transitioned. The row enable signal LT isinputted into the voltage level control circuit 1 and the row decoder 6.

FIG. 2 is a timing chart illustrative of an operation of the circuitshown in FIG. 1 in a stand-by mode. An operation of generating a boostvoltage for refreshing memory cells will hereinafter be described withreference to FIGS. 1 and 2.

If the pseudo-SRAM is placed in the stand-by state, then the refreshsignal is outputted from the refresh timing generation circuit 7 at aconstant cycle, for example, 16 microseconds, and then the refreshsignal is supplied to the row enable generation circuit 8. The rowenable generation circuit 8 generates receives an input of the refreshsignal and generates a row enable signal LT and then supplies the rowenable signal LT to the voltage level control circuit 1. The voltagelevel control circuit 1 is activated by the row enable signal LT,whereby the voltage level control circuit 1 compares the boost voltageVbt to the first and second reference voltages Vref1 and Vref2. If theboost voltage Vbt is lower than the first reference voltage Vref1, thenthe internal voltage level control signal “A” becomes “H” (high level),whereby the ring oscillator 3 starts an oscillation and supplies theoscillation output “B” to the boost circuit 4.

The boost circuit 4 boosts the boost voltage Vbt by using theoscillation output “B”. After the boost voltage Vbt is boosted to reachthe same level as the second reference voltage Vref2, then the voltagelevel control circuit 1 sets the internal voltage level control signal“A” at “L” (low level), whereby the oscillation of the ring oscillator 3is discontinued, and thus the boosting operation of the boost circuit 4is discontinued. During this cycle, the refresh operation is executed tothe memory cells in the memory cell array 2.

In the stand-by mode, the refresh timing signal is automaticallygenerated at a cycle which ensures holding data, together with placingthe voltage level control circuit 1 into the power ON state, in order tohold the word level at not less than the reference voltage Vref1. Exceptwhen the refresh timing, the voltage level control circuit 1 is placedinto the power OFF, in order to both ensure the data hold and reduce theconsumption of current.

The pseudo SRAM is transitioned from the stand-by state into the activestate, so that the chip select signal CS is risen and then theread/write address Add is then transitioned, whereby the row enablegeneration circuit 8 detects this transition and outputs the signal LTfor activating the voltage level control circuit 1. Accordingly, in theactive state, boosting operation of the boost voltage Vbt is made everytime accesses to memory cells are made.

FIG. 3 is a block diagram illustrative of an example of a configurationof a conventional timing cycle generation circuit in the refresh timinggeneration circuit. The timing cycle generation circuit comprises anOR-gate 11 and a timer circuit 12, wherein the OR-gate 11 receivesinputs of both an operation mode selecting signal MODE for switchingbetween a deep stand-by mode and a stand-by mode and a chip selectsignal CS, and the timer circuit 12 receives an output from the OR-gate11 and outputs a timer signal TN with a constant cycle for refreshoperation when the output signal is “H” (high level). A self-refreshcycle of the memory cells in the stand-by mode is set by this timersignal TN.

FIG. 4 is a timing chart illustrative of an operation of the pseudo-SRAMshown in FIG. 1, which incorporates the timing cycle generation circuitshown in FIG. 3.

As shown in FIG. 4, in the deep stand-by mode, any power supply to thepseudo-SRAM shown in FIG. 1 is completely discontinued. Any power supplyto the circuit necessary for refresh is also discontinued. Thus, theboost voltage Vbt of the boost circuit 4 is lowered almost to the groundpotential. By switching the deep stand-by mode into the stand-by mode,the power supply to the pseudo-SRAM shown in FIG. 1 is re-started andthus the power supply to the circuit necessary for refresh is also made,whereby the refresh timing generation circuit 7 outputs refresh signalsat a constant cycle, and the boost voltage Vbt of the boost circuit 4 isalso increased.

The transition to the stand-by state is completed when the boost voltageVbt is risen up to the first reference voltage Vref1, thereby enablingany active operations such as accesses to the memory. As shown in FIG.4, however, it takes a time that the boost voltage Vbt lowered down toalmost the ground potential in the deep stand-by mode is risen up to thefirst reference voltage Vref1 in the stand-by state.

Normally, a time of approximately 200 microseconds is set for boostingthe voltage as the stand-by time until he pseudo-SRAM is started up andplaced into an memory accessible state. During this time, any activeoperations are inhibited.

In the future, the necessary memory capacity will be further increased.In this case, a load to the boost circuit is also further increased,thereby making longer a time to rise up to the stand-by state. It isestimated that a voltage rising time of 200 micrometers is insufficientfor rising up to the stand-by mode.

DISCLOSURE OF INVENTION

Accordingly, in view of the above issues, it is an object of the presentinvention to provide a semiconductor memory device having a firstoperation mode of completely discontinuing any power supplies topredetermined circuits, and a second operation mode of a power supply tothe predetermined circuits, wherein the semiconductor memory device iscapable of shortening a time necessary for transition from the firstoperation mode without the power supply into the second operation modewith the power supply.

It is a further object of the present invention to provide a timingcycle generation circuit provided in a semiconductor memory devicehaving a first operation mode of completely discontinuing any powersupplies to predetermined circuits, and a second operation mode of apower supply to the predetermined circuits, wherein the timing cyclegeneration circuit is capable of shortening a time necessary fortransition from the first operation mode without the power supply intothe second operation mode with the power supply.

It is a still further object of the present invention to provide asemiconductor memory device capable of performing a transition operationfrom a deep stand-by mode to a stand-by mode at a shortened transitiontime, along with a high speed operation of voltage boosting up to arefresh-enabling voltage level by using a shorter time cycle than atimer cycle, which is used for supplying cyclically a refresh voltage toa memory in the stand-by mode.

It is yet a further object of the present invention to provide a timingcycle generation circuit capable of performing a transition operationfrom a deep stand-by mode to a stand-by mode at a shortened transitiontime, along with a high speed operation of voltage boosting up to arefresh-enabling voltage level by using a shorter time cycle than atimer cycle, which is used for supplying cyclically a refresh voltage toa memory in the stand-by mode.

It is a furthermore object of the present invention to provide asemiconductor memory device capable of performing a transition operationfrom a power-off state to a stand-by mode of a power-on state at ashortened transition time, by using a shorter time cycle than a timercycle, which is used in the stand-by mode.

It is moreover object of the present invention to provide a timing cyclegeneration circuit capable of performing a transition operation from apower-off state to a stand-by mode of a power-on state at a shortenedtransition time, by using a shorter time cycle than a timer cycle, whichis used in the stand-by mode.

It is still more object of the present invention to provide a timingcycle generation circuit capable of selectively supplying a first timercycle used in a first operation mode of allowing an internal circuit toperform a specific operation, and a second timer cycle being shorterthan the first timer cycle, and the second timer cycle being selectivelyused only in transition operation to the first operation mode from otherstate than the first operation mode.

It is yet more object of the present invention to provide a timing cyclegeneration circuit capable of selectively supplying a first timer cycleused in a first operation mode of allowing an internal circuit toperform a specific operation, and a second timer cycle being shorterthan the first timer cycle, and the second timer cycle being selectivelyused only in transition operation with voltage boost or drop to thefirst operation mode from other state than the first operation mode.

Accordingly, the present invention provides a semiconductor memorydevice having a plurality of operation modes, wherein the semiconductormemory device includes: a first cycle generation circuit for generatingtiming pulses of a first cycle; a second cycle generation circuit forgenerating timing pulses of a second cycle which is shorter than thefirst cycle; an internal voltage generation circuit for generating apredetermined internal voltage upon receiving inputs of the timingpulses from the first or second cycle generation circuit ; and a timingpulse switching circuit for selecting the timing pulses from the secondcycle generation circuit and supplying the selected timing pulses to theinternal voltage generation circuit when the semiconductor memory deviceis transitioned from a first operation mode to a second operation modein the plurality of operation modes.

The semiconductor memory device may further include a control circuitfor outputting first, second and third control signals in accordancewith an operation mode selecting signal which selects a single operationmode in the plurality of operation modes. The first and second cyclegeneration circuits. are controlled in operation and non-operationindependently in accordance with the first and second control signals,respectively, and the timing pulse switching circuit selects the timingpulses of either one of the first and second cycle generation circuitsin accordance with the third control signal.

The control circuit may include a counter circuit for counting thetiming pulses outputted from the second cycle generation circuit, andoutputting the third control signal when a counted value becomes apreviously set value.

The first operation mode may be an operation mode of discontinuing apower supply to a predetermined circuit of the semiconductor memorydevice, and the second operation mode may be an operation mode ofsupplying a power to the predetermined circuit.

The predetermined circuit may comprise a circuit necessary for refreshof memory cells of the semiconductor memory device.

The first cycle may be a cycle of refreshing memory cells of thesemiconductor memory device.

The first operation mode may be an operation mode of not ensuring datahold stored in memory cells of the semiconductor memory device, and thesecond operation mode may be an operation mode of ensuring data holdstored in memory cells of the semiconductor memory device.

The internal voltage generation circuit may comprise a boost voltagegeneration circuit for generating a boost voltage to be applied to wordlines of memory cells of the semiconductor memory device.

The internal voltage generation circuit may comprise an internal voltagedown circuit for dropping an external power voltage and supplies thedropped power voltage to an internal circuit.

The internal voltage generation circuit may comprise a substrate backbias generation circuit for supplying a semiconductor substrate with aback bias voltage lower than a ground level.

The semiconductor memory device may comprise a pseudo-SRAM as oneexample.

The semiconductor memory device may, for example, be applicable to aportable electronic device.

The present invention further provides a semiconductor memory devicehaving a plurality of memory cells, and having a stand-by mode ofsupplying a power to a circuit necessary for refreshing memory cells soas to ensure data hold stored in the memory cells, and a deep stand-bymode of discontinuing a power supply to the circuit necessary forrefreshing memory cells so as not to ensure data hold stored in thememory cells, wherein the semiconductor memory device includes : aninternal voltage generation circuit being so operated as synchronizingwith a refresh cycle for generating a predetermined internal voltage ;and a timing cycle generation circuit for controlling an operation cycleof the internal voltage generation circuit, and wherein the timing cyclegeneration circuit includes: a first timer circuit for setting so thatthe operation cycle of the internal voltage generation circuitsynchronizes with the refresh cycle in the stand-by mode; and a secondtimer circuit operated in a transition from the deep stand-buy mode tothe stand-by mode for setting so that the operation cycle of theinternal voltage generation circuit is a cycle shorter than the refreshcycle, for making the internal voltage into a predetermined voltagelevel at a short time.

The timing cycle generation circuit further includes : an OR-gatereceiving an input of an operation mode selecting signal for switchingthe deep stand-by mode and the stand-by mode and also another input of achip select signal ; the first timer circuit being operated, when theOR-gate receives an input of either the operation mode selecting signalor the chip select signal, so that the first timer circuit outputs atimer signal synchronizing with the refresh cycle ; a logic circuitreceiving both the operation mode selecting signal and an output from aone-shot pulse generation circuit, and the logic circuit outputting afirst level signal when the operation mode selecting signal istransitioned from the deep stand-by mode into the stand-by mode, and thelogic circuit outputting a second level signal upon receipt of theoutput from the one-shot pulse generation circuit ; the second timercircuit being operated, when the logic circuit outputs the first levelsignal, so that the second timer circuit outputs a timer signal with ashorter cycle than the refresh cycle ; a counter circuit being re-set bya rising edge, to the first level, of the output from the logic circuitfor counting a timer signal outputted from the second timer circuit, andthe counter circuit outputting a timer output switching signal when acounted value reaches a previously set value; a selecting circuitreceiving the timer output switching signal from the counter circuit,and the selecting circuit selecting either one of the timer signals fromthe first and second timer circuits for outputting selected one as atimer signal ; and the one-shot pulse generation circuit receiving thetimer output switching signal from the counter circuit, and the one-shotpulse generation circuit supplying one-shot pulse to the logic circuit.

The timing cycle generation circuit may further include: an OR-gatereceiving an input of an operation mode selecting signal for switchingthe deep stand-by mode and the stand-by mode and also another input of achip select signal ; the first timer circuit being operated, when theOR-gate receives an input of either the stand-by mode signal or the chipselect signal, so that the first timer circuit outputs a timer signalsynchronizing with the refresh cycle ; a logic circuit receiving boththe operation mode selecting signal and the chip select signal, and thelogic circuit outputting a first logic level signal when the operationmode selecting signal is transitioned from the deep stand-by mode intothe stand-by mode, and the logic circuit outputting a second logic levelsignal upon receipt of the chip select signal; the second timer circuitbeing operated, when the logic circuit outputs the first logic levelsignal, so that the second timer circuit outputs a timer signal with ashorter cycle than the refresh cycle; and a selecting circuit forselecting and outputting either one of the timer signals from the firstand second timer circuits in accordance with an output level from thelogic circuit.

The internal voltage generation circuit may comprise a boost voltagegeneration circuit for generating a boost voltage to be applied to wordlines of memory cells of the semiconductor memory device.

The internal voltage generation circuit may comprise an internal voltagedown circuit for dropping an external power voltage and supplies thedropped power voltage to an internal circuit.

The internal voltage generation circuit may comprise a substrate backbias generation circuit for supplying a semiconductor substrate with aback bias voltage lower than a ground level.

The semiconductor memory device may comprise a pseudo-SRAM as oneexample.

The semiconductor memory device may, for example, be applicable to aportable electronic device.

The present invention further provides a semiconductor memory devicehaving a plurality of memory cells, and having a stand-by mode ofsupplying a power to a circuit necessary for refreshing memory cells soas to ensure data hold stored in the memory cells, wherein thesemiconductor memory device includes : an internal voltage generationcircuit being so operated as synchronizing with a refresh cycle forgenerating a predetermined internal voltage ; and a timing cyclegeneration circuit for controlling an operation cycle of the internalvoltage generation circuit, and wherein the timing cycle generationcircuit further includes : a first timer circuit for setting so that theoperation cycle of the internal voltage generation circuit synchronizeswith the refresh cycle in the stand-by mode ; and a second timer circuitoperated in a transition from a power OFF state to a power ON state forsetting so that the operation cycle of the internal voltage generationcircuit is a cycle shorter than the refresh cycle, for making theinternal voltage into a predetermined voltage level at a short time.

The timing cycle generation circuit may further include: an OR-gatereceiving an input of a power ON signal and another input of a chipselect signal ; the first timer circuit being operated, when the OR-gatereceives the power ON signal and the chip select signal, so that thefirst timer circuit outputs a timer signal synchronizing with therefresh cycle; a logic circuit receiving both the power ON signal and anoutput from a one-shot pulse generation circuit; the second timercircuit being operated, when the logic circuit outputs the first levelsignal, so that the second timer circuit outputs a timer signal with ashorter cycle than the refresh cycle; a counter circuit being re-set bya transition signal which represents that the output from the logiccircuit is transitioned to the first logic level for counting a timersignal outputted from the second timer circuit, and the counter circuitoutputting a timer output switching signal when a counted value reachesa previously set value ; a selecting circuit receiving the timer outputswitching signal from the counter circuit, and the selecting circuitselecting either one of the timer signals from the first and secondtimer circuits for outputting selected one as a timer signal ; and theone-shot pulse generation circuit receiving the timer output switchingsignal from the counter circuit, and the one-shot pulse generationcircuit supplying one-shot pulse to the logic circuit.

The timing cycle generation circuit may further include: an OR-gatereceiving an input of a power ON signal and another input of a chipselect signal; the first timer circuit being operated, when the OR-gatereceives the power ON signal and the chip select signal, so that thefirst timer circuit outputs a timer signal synchronizing with therefresh cycle ; a logic circuit outputting a first logic level signalupon receipt of the power ON signal, and the logic circuit outputting asecond logic level signal upon receipt of the chip select signal ; thesecond timer circuit being operated, when the logic circuit outputs thefirst logic level signal, so that the second timer circuit outputs atimer signal with a shorter cycle than the refresh cycle; and aselecting circuit for selecting and outputting either one of the timersignals from the first and second timer circuits in accordance with anoutput level from the logic circuit.

The internal voltage generation circuit may comprise a boost voltagegeneration circuit for generating a boost voltage to be applied to wordlines of memory cells of the semiconductor memory device.

The internal voltage generation circuit may comprise an internal voltagedown circuit for dropping an external power voltage and supplies thedropped power voltage to an internal circuit.

The internal voltage generation circuit may comprise a substrate backbias generation circuit for supplying a semiconductor substrate with aback bias voltage lower than a ground level.

The semiconductor memory device may comprise a pseudo-SRAM as oneexample.

The semiconductor memory device may, for example, be applicable to aportable electronic device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrative of one example of the structureof the essential part of the conventional pseudo-SRAM.

FIG. 2 is a timing chart describing operations in stand-by mode of thecircuits shown in FIG. 1.

FIG. 3 is a block diagram illustrative of an example of a configurationof the conventional timing cycle generation circuit in the refreshtiming generation circuit.

FIG. 4 is a timing chart illustrative of an operation of the pseudo-SRAMshown in FIG. 1, which incorporates the timing cycle generation circuitshown in FIG. 3.

FIG. 5 is a block diagram illustrative of a configuration of a timingcycle generation circuit in accordance with the first embodiment of thepresent invention.

FIG. 6 is a block diagram illustrative of one example of a structure ofan essential part of a known pseudo-SRAM, to which a timing cyclegeneration circuit is applicable in accordance with the first embodimentof the present invention.

FIG. 7 is a timing chart illustrative of an operation of the pseudo-SRAMshown in FIG. 6, which incorporates the timing cycle generation circuitshown in FIG. 5 in accordance with the first embodiment.

FIG. 8 is a block diagram illustrative of a configuration of a timingcycle generation circuit in accordance with the second embodiment of thepresent invention.

FIG. 9 is a timing chart illustrative of an operation of the pseudo-SRAMshown in FIG. 6, which incorporates the timing cycle generation circuitshown in FIG. 8 in accordance with the second embodiment.

FIG. 10 is a circuit diagram of the timing cycle generation circuitapplied to an internal voltage down circuit for reducing an externalpower voltage and supplies the reduced power voltage to an internalcircuit, in accordance with one embodiment of the present invention.

FIG. 11 is a timing chart illustrative of an operation of the timingcycle generation circuit shown in FIG. 8 applied to the internal voltagedown circuit shown in FIG. 10 in accordance with the second embodiment.

FIG. 12 is block diagram illustrative of an embodiment, wherein thetiming cycle generation circuit according to the present invention isapplied to a substrate back bias generation circuit for supplying a backbias lower than a ground level to a semiconductor substrate.

FIG. 13 is a circuit diagram illustrative of a typical example of theback bias generation circuit shown in FIG. 12.

FIG. 14 is a timing chart showing a summary of operations of the backbias generation circuit shown in FIG. 13.

THE BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will, hereinafter, be described.

(First Embodiment)

The first embodiment of the present invention provides a timing cyclegeneration circuit provided n a semiconductor memory device having afirst stand-by mode of completely discontinuing any power supply to apredetermined circuit and a second stand-by mode of supplying a power tosaid predetermined circuit. FIG. 5 is a block diagram illustrative of aconfiguration of a timing cycle generation circuit in accordance withthe first embodiment of the present invention.

The timing cycle generation circuit has the following circuitconfiguration. The timing cycle generation circuit includes an OR-gate11, a first timer circuit 12, a logic circuit 13, a second timer circuit14, a counter circuit 15, a one-shot pulse generation circuit 16 and aselector circuit 17.

The OR-gate 11 receives an input of an operation mode selecting signalMODE which switches a deep stand-by mode and a stand-by mode and anotherinput of a chip select signal CS. The OR-gate 11 outputs a logical OR ofthe operation mode selecting signal MODE and the chip select signal CS.An output from the OR-gate 11 is then inputted into the first timercircuit 12. If the output from the OR-gate 11 is “H” (high level), thenthe first timer circuit 12 is operated to output a timer signal TN of afirst cycle (16 microseconds).

The logic circuit 13 receives the operation mode selecting signal MODEand an output signal from the one-shot pulse generation circuit 16, sothat the logic circuit 13 outputs a logic output G which is theninputted into the second timer circuit 14. If the logic output G fromthe logic circuit 13 is “H” (high level), then the second timer circuit14 is operated to output another timer signal TR of a second cycleshorter than the first cycle. The timer signal TR of the second cyclefrom the second timer circuit 14 and the logic output G from the logiccircuit 13 are inputted into the counter circuit 15. The counter circuit15 is re-set by a transition of the logic output G from the logiccircuit 13 to “H” (high level), so that the counter circuit 15 countsthe timer signal TR from the second timer circuit 14. If the countedvalue reaches a previously set value, then the counter circuit 15outputs a timer output switching signal C of “H” (high level). The timeroutput switching signal C outputted form the counter circuit 15 is thensupplied to both the one-shot pulse generation circuit 16 and theselector circuit 17.

The selector circuit 17 may comprise a multiplexer (MUX). The selectorcircuit 17 receives the timer output switching signal C outputted formthe counter circuit 15, so that based on the timer output switchingsignal C, the selector circuit 17 selects either one of the timer signalTN of the first cycle outputted from the first timer circuit 12 and thetimer signal TR of the second cycle outputted from the second timercircuit 14, whereby the selector circuit 17 outputs the selected one asa timer output TO. The one-shot pulse generation circuit 16 receives thetimer output switching signal C form the counter circuit 15, so that theone-shot pulse generation circuit 16 outputs one-shot pulse D. Theone-shot pulse D is then inputted into the logic circuit 13, so that thelogic circuit 13 receives both the operation mode selecting signal MODEand the logic circuit 13 and outputs the logic output G.

The second cycle of the timer signal TR outputted from the second timercircuit 14 is set shorter than the first cycle of the timer signal TNoutputted from the first timer circuit 12. Thus, the timer signal TN ofthe first cycle outputted from the first timer circuit 12 is a timersignal to be used in the normal operation, while the timer signal TR ofthe second cycle outputted from the second timer circuit 14 is anothertimer signal to be used only in a time period of needing a high speedoperation.

Accordingly, the above-described novel timing cycle generation circuitof the present invention has a novel circuit configuration ofselectively supplying one of the timer signal TN of the first cycle andthe timer signal TR of the second cycle shorter than the first cycle,wherein the timer signal TN is used in the first operation mode, inwhich the internal circuit performs a specific operation such as arefresh operation, and the timer signal TR is used selectively in atransition from other state than the first operation mode into the firstoperation mode, for example, in voltage-boosting operation orvoltage-down operation. The internal circuit is capable of taking aspecific operation mode of performing a specific operation, and otherstate than this specific operation mode, provided that any transitiontime is present from the other state than the specific operation modeinto the specific operation mode. If it is necessary or desired toshorten the transition time, then the above-described novel timing cyclegeneration circuit of the present invention is applicable.

For example, in case that the above-described novel timing cyclegeneration circuit is applied to a pseudo-SRAM as one example of theinternal circuit, the timer signal TN of the first cycle outputted fromthe first timer circuit 12 is used for cyclic refresh operations in thestand-by mode, while the timer signal TR of the second cycle outputtedfrom the second timer circuit 14 is used but only in the transition timefrom the deep stand-by mode to the stand-by mode, or in the transitiontime from the power ON time into the stand-by mode, for high speedvoltage adjustment to a voltage level enabling refresh operation,resulting in a shortened switching time from the deep stand-by mode orthe power ON time into the stand-by mode.

There is no need to limit the circuit configuration of the pseudo-SRAM,to which the timing cycle generation circuit is applicable. For example,the timing cycle generation circuit is applicable to the pseudo-SRAMshown in FIG. 1. In order to demonstrate the usefulness of the noveltiming cycle generation circuit in accordance with the presentinvention, the following descriptions will focus on one typical examplethat the timing cycle generation circuit is applied to the knownpseudo-SRAM as the internal circuit.

FIG. 6 is a block diagram illustrative of one example of a structure ofan essential part of the known pseudo-SRAM, to which the timing cyclegeneration circuit is applicable in accordance with the first embodimentof the present invention. The essential part of the pseudo-SRAM shown inFIG. 6 is almost identical in configuration to the essential part of thepseudo-SRAM shown in FIG. 1, except for a configuration of a refreshtiming generation circuit 70.

In FIG. 6, a voltage level control circuit 1 generates an internalvoltage level control signal “A” based on first and second referencevoltages Vref1 and Vref2. This internal voltage level control signal “A”is a signal for controlling a level of a boost voltage Vbt to be appliedto word lines of a memory cell array 2. The internal voltage levelcontrol signal “A” is outputted from the voltage level control circuit 1and then inputted into a ring oscillator 3. The ring oscillator 3 isactivated and oscillated by “H” (high level) of the internal voltagelevel control signal “A” from the voltage level control circuit 1,whereby the ring oscillator 3 outputs an oscillation output “B”. Theoscillation output “B” outputted from the ring oscillator 3 is theninputted into a boost circuit 4.

The boost circuit 4 comprises a charge pump circuit for generating theboost voltage Vbt as an internal voltage. The boost circuit 4 boostsstep-by-step a power voltage VDD by utilizing the oscillation output “B”outputted from the ring oscillator 3 for generating the boost voltageVbt. This boost voltage Vbt is then inputted into a word decoder 5 fordriving a word line. The boost voltage Vbt is set at a level which ishigher than the power voltage VDD, for example, about VDD+1.5V toVDD+2V. The word decoder 5 supplies the boost voltage Vbt to a word lineselected by an output from a row decoder 6. The memory cell array 2comprises the same configuration as the memory cell array of DRAM.

A refresh timing generation circuit 70 generates a refresh signal and arefresh address, wherein the refresh signal is to refresh memory cellsin the memory cell array 2 at a constant time interval, while therefresh address is to designate an address of a memory cell which shouldbe refreshed. The refresh timing generation circuit 70 includes theabove-described timing cycle generation circuit shown in FIG. 5, whereinthe timer output (TO) is inputted as a refresh signal into a row enablegeneration circuit 8. The refresh address is outputted from the refreshtiming generation circuit 70 and then inputted into the row decoder 6.The row enable generation circuit 8 generates a row enable signal LT ata timing when the refresh timing generation circuit 70 generates therefresh signal.

The row enable generating circuit 8 receives inputs of a write enablesignal WE, a chip select signal CS and a read/write address Add of thememory cell array 2, and the row enable generating circuit 8 outputs therow enable signal LT every time the read/write address Add istransitioned. The row enable signal LT is inputted into the voltagelevel control circuit 1 and the row decoder 6.

The above-described circuits of the pseudo-SRAM are operated based onthe timer output TO outputted from the novel timing cycle generationcircuit described with reference to FIG. 5.

FIG. 7 is a timing chart illustrative of an operation of the pseudo-SRAMshown in FIG. 6, which incorporates the timing cycle generation circuitshown in FIG. 5 in accordance with the first embodiment. Operations ofthe pseudo-SRAM will, hereinafter, be described with reference to FIGS.5 through 7.

In the deep stand-by mode, a power supply is made to only the circuitwhich needs the power supply, while a power for the timing cyclegeneration circuit remains OFF-state, and the boost voltage Vbt islowered at the ground potential. When this deep-stand-by mode istransitioned to the stand-by mode, then a power supply is made to thetiming cycle generation circuit, whereby the operation mode selectingsignal MODE becomes “H” (high level), and the logic output G from thelogic circuit 13 becomes “H” (high level). The first and second timercircuits 12 and 14 are started, so that the timer signal TN of the firstcycle is outputted from the first timer circuit 12, and the timer signalTR of the second cycle is outputted from the second timer circuit 14.

At the time when the operation mode selecting signal MODE becomes “H”(high level), the timer output switching signal C outputted from thecounter circuit 15 is still “L” (low level). The logic output G from thelogic circuit 13 is transitioned to “H” (high level), whereby thecurrent count value of the counter circuit 15 is re-set, so that thecounter circuit 15 counts the timer signal TR of the second cycleoutputted from the second timer circuit 14. If the counted value of thecounter circuit 15 becomes identical with the previously set value, thenthe timer output switching signal C outputted from the counter circuit15 is transitioned to “H” (high level). The timer output switchingsignal C as a timer switching control signal from the counter circuit 15is then inputted into the selector circuit 17.

If the timer output switching signal C from the counter circuit 15 is“H” (high level), the multiplexer of the selector circuit 17 selects andoutputs the timer signal TR of the second cycle outputted from thesecond timer circuit 14. If the timer output switching signal C from thecounter circuit 15 is “L” (low level), the multiplexer of the selectorcircuit 17 selects and outputs the timer signal TN of the first cycleoutputted from the first timer circuit 12. Immediately after the deepstand-by mode is transitioned into the stand-by mode, then the timersignal TR of the second cycle from the second timer circuit 14 isselected by and outputted from the selector circuit 17, wherein thesecond timer circuit 14 is to output timing signals of shorter cyclethan a self-refresh cycle. The boost circuit 4 shown in FIG. 6 executesa boost operation by the timer signal TR of the second cycle shorterthan the refresh cycle, whereby the output voltage Vbt from the boostcircuit 4 is returned at a high speed to a voltage level necessary forrefreshing memory cells.

Thereafter, the counted value of the counter circuit 15 becomes apreviously set value, and the timer output switching signal C outputtedfrom the counter circuit 15 is transitioned to “H” (high level), so thatthe multiplexer of the selector circuit 17 selects and outputs the timersignal TN of the first cycle outputted from the first timer circuit 12.In the subsequent stand-by mode, the output voltage from the boostcircuit 4 is maintained at the predetermined voltage by the timer signalTN of the first cycle of 16 microseconds which is needed forself-refresh operation, whereby the refresh operation is executed to thememory cells for ensuring data hold of the memory in the stand-by mode.

The timer output switching signal C outputted from the counter circuit15 is also inputted into the one-shot pulse generation circuit 16. Theone-shot pulse generation circuit 16 outputs the one-shot pulse D at atime when the timer output switching signal C is transitioned to “H”(high level). The one-shot pulse D is also inputted into the logiccircuit 13, whereby the logic output G from the logic circuit 13 istransitioned to “L” (low level), whereby any current supply to the timer14 is discontinued to suppress unnecessary consumption of current.

In accordance with this embodiment, the above descriptions have beenmade to the operations in transition from the deep stand-by mode to thestand-by mode. Notwithstanding, the timing cycle generation circuit ofthe present invention is applicable to the operation of boosting theboost voltage upon power ON to a device incorporating the pseudo-SRAM.In this case, the power-ON signal is used instead of the operation modeselecting signal MODE.

In accordance with the present embodiment, at the time either of thetransition from the deep stand-by mode to the stand-by mode or of thepower ON, the high speed voltage boosting operation up to such a voltagelevel as enabling refresh operation is executed by the timer cycleshorter than the timer cycle used for cyclically supplying the refreshvoltage to the memory in the stand-by mode, thereby shortening thetransition time from either the deep stand-by mode or the power-ON tothe stand-by mode.

It is also possible to eliminate the second time circuit 14 operated atthe transition from the deep stand-by mode to the stand-by mode or atthe power-ON, while the timing cycle is controlled of the first timercircuit 12 used for cyclically supplying the refresh voltage to thememory in the stand-by mode, so that only the first timer circuit 12generates the refresh cycle and the timing signal of the shorter cyclethan this refresh cycle. In general, the timer generator comprises ananalogue circuit which takes a time for changing the cycle. In order torealize a quick switch of the timing cycle, the use of the independentcycle generation means is effective in accordance with the presentinvention.

It is also possible to allow the transition to the stand-by mode withinthe above-described time as set if an increase in capacity of the memoryof the device is needed, wherein the device has the stand-by modeensuring the data hold of the memory cells and the deep stand-by mode ofnot ensuring the data hold of the memory cells, and the transition timehas previously been set from either the deep stand-by mode or the powerON to the stand-by mode.

The above-described stand-by mode and deep stand-by mode are effectiveto suppress the consumption of power. For example, the semiconductormemory device having the above-described stand-by mode and deep stand-bymode is effectively applicable to portable electronic devices.Accordingly, the above-described timing cycle generation circuit iseffectively applicable to semiconductor memory devices integrated inportable electronic devices.

(Second Embodiment)

The second embodiment of the present invention will, hereinafter, bedescribed.

FIG. 8 is a block diagram illustrative of a timing cycle generationcircuit in accordance with the second embodiment of the presentinvention.

The timing cycle generation circuit of the present invention comprisesan OR-gate 11 which receives an input of an operation mode selectingsignal MODE which switches a deep stand-by mode and a stand-by mode andanother input of a chip select signal CS, a first timer circuit 12 whichis operated upon “H” (high level) of the output from the OR-gate 11 foroutputting a timer signal TN of a first cycle (16 microseconds), a logiccircuit 18 which receives an input of the operation mode selectingsignal MODE and another input of the chip select signal CS, a secondtimer circuit 14 which is operated upon “H” (high level) of the outputfrom the logic circuit 18 for outputting a timer signal TR of a secondcycle shorter than the first cycle, and a selector circuit 17 whichselects either one signal from the first timer circuit 12 and the secondtimer circuit 14 based on the logic output G from the logic circuit 18and outputs the selected one as the timer output TO. The selectorcircuit 17 may comprise a multiplexer (MUX).

FIG. 9 is a timing chart illustrative of an operation of the pseudo-SRAMshown in FIG. 6, which incorporates the timing cycle generation circuitshown in FIG. 8 in accordance with the second embodiment. Operations ofthe pseudo-SRAM will, hereinafter, be described with reference to FIGS.6, 8 and 9.

In the deep stand-by mode, a power supply is made to only the circuitwhich needs the power supply, while a power for the timing cyclegeneration circuit remains OFF-state, and the boost voltage Vbt islowered at the ground potential. When this deep-stand-by mode istransitioned to the stand-by mode, then a power supply is made to thetiming cycle generation circuit, whereby the operation mode selectingsignal MODE becomes “H” (high level), and the output from the OR-gate 11and the logic output G from the logic circuit 13 become “H” (highlevel). The first and second timer circuits 12 and 14 are started, sothat the timer signal TN of the first cycle is outputted from the firsttimer circuit 12, and the timer signal TR of the second cycle isoutputted from the second timer circuit 14.

The logic output G from the logic circuit 18 is inputted into themultiplexer of the selector circuit 17 as the timer switching controlsignal. If the logic output G from the logic circuit 18 is “H” (highlevel), the multiplexer of the selector circuit 17 selects and outputsthe timer signal TR of the second cycle outputted from the second timercircuit 14. If the logic output G from the logic circuit 18 is “L” (lowlevel), the multiplexer of the selector circuit 17 selects and outputsthe timer signal TN of the first cycle outputted from the first timercircuit 12.

Immediately after the deep stand-by mode is transitioned into thestand-by mode, then the timer signal TR of the second cycle from thesecond timer circuit 14 is selected and outputted. The boost circuit 4shown in FIG. 6 executes a boost operation by the timer signal TR of thesecond cycle shorter than the refresh cycle, whereby the output voltageVbt from the boost circuit 4 is returned at a high speed to a voltagelevel necessary for refreshing memory cells.

Thereafter, the chip select signal CS is transitioned to “H” (highlevel) for entry into the active mode, so that the multiplexer of theselector circuit 17 selects and outputs the timer signal TN of the firstcycle outputted from the first timer circuit 12. The logic output G fromthe logic circuit 18 is transitioned from “L” (low level) to “H” (highlevel) only when the operation mode selecting signal MODE istransitioned from “L” (low level) to “H” (high level). If the chipselect signal CS is thereafter transitioned to “L” (low level) fortransition from the active mode to the stand-by mode, then the logicoutput G from the logic circuit 18 remains “L” (low level), whereby thesecond timer circuit 14 is not yet started.

In the subsequent switch between the stand-by mode and the active mode,the multiplexer of the selector circuit 17 selects and outputs the timersignal TN of the first cycle outputted from the first timer circuit 12.The boosting operation is executed by the boost circuit 4 based on thetimer signal TN of the first cycle of 16 microseconds which is neededfor self-refresh operation, whereby the output voltage from the boostcircuit 4 is boosted up to the predetermined voltage and thenmaintained. Any self-refresh operation in the subsequent stand-by modeis normally executed for ensuring data hold of the memory.

In accordance with this embodiment, the above descriptions have beenmade to the operations in transition from the deep stand-by mode to thestand-by mode. Notwithstanding, the timing cycle generation circuit ofthe present invention is applicable to the operation of boosting theboost voltage upon power ON to a device incorporating the pseudo-SRAM.In this case, the power-ON signal is used instead of the operation modeselecting signal MODE.

In accordance with the present embodiment, the second timer circuit 14continues its operation for continuously supplying the current until thefirst input of the chip select signal CS appears after the deep stand-bymode or the power ON state is transitioned to the stand-by mode. Thiscontinuous supply of the current causes a somewhat increase of theconsumption of current as compared to the above first embodiment.Notwithstanding, it is possible to shorten the transition time fromeither the deep stand-by mode or the power-ON to the stand-by mode.

It is also possible to allow the transition to the stand-by mode withinthe above-described time as set if an increase in capacity of the memoryof the device is needed, wherein the device has the stand-by modeensuring the data hold of the memory cells and the deep stand-by mode ofnot ensuring the data hold of the memory cells, and the transition timehas previously been set from either the deep stand-by mode or the powerON to the stand-by mode.

FIG. 10 is a circuit diagram of the timing cycle generation circuitapplied to an internal voltage down circuit for reducing an externalpower voltage and supplies the reduced power voltage to an internalcircuit, in accordance with one embodiment of the present invention.

The internal voltage down circuit includes a differential amplifier 22and a p-channel MOS field effect transistor 23 (hereinafter referred toas “PMOS transistor”). An inversion input terminal of the differentialamplifier 22 receives an input of a reference voltage VREF, while anon-inversion input terminal of the differential amplifier 22 receivesan input of an internal voltage VINT. A source electrode of the PMOStransistor is connected to an external power voltage VDD, while a gateelectrode thereof receives an output signal from the differentialamplifier 22, and a drain electrode thereof outputs an internal voltageVINT which is a voltage reduced from the external power voltage VDD. Theinternal voltage VINT, which is a voltage reduced from the externalpower voltage VDD, appears on an output line of the internal voltagedown circuit. This output line of the internal voltage down circuit isconnected to an internal circuit 21, so that the voltage-reducedinternal voltage VINT is supplied to the internal circuit 21. Theinternal circuit 21 may include, but not limited to, semiconductormemory devices such as DRAM and pseudo-SRAM.

The differential amplifier 22 comprises an n-channel MOS field effecttransistor 25 (hereinafter referred to as NMOS transistor) with a gatereceiving an input of the reference voltage VREF, an NMOS transistor 26with a gate receiving an input of the internal voltage VINT, a currentsource NMOS transistor 24 connected between a common source electrode ofthe NMOS transistors 25 and 26 and a ground potential, and a pair ofPMOS transistors 26 and 27 constituting a current mirror, which areconnected between respective drain electrodes of the NMOS transistors 25and 26 and the external power voltage VDD. The drain electrode of theNMOS transistor 25 is connected to the gate electrode of thevoltage-down PMOS transistor 23.

This differential amplifier 22 compares the internal voltage VINT on theoutput line to the reference voltage VREF. If the internal voltage VINTis lower than the reference voltage VREF, then the output voltage fromthe differential amplifier 22 or the drain voltage of the NMOStransistor 25 is dropped, whereby the PMOS transistor 23 is transitionedto ON-state, thereby increasing the current from the external powervoltage VDD, and increasing the internal voltage VINT.

If the internal voltage VINT is higher than the reference voltage VREF,then the output voltage from the differential amplifier 22 is increased,whereby the PMOS transistor 23 is transitioned to OFF-state, therebydecreasing the current from the external power voltage VDD, anddecreasing the internal voltage VINT. Namely, the differential amplifier22 shows a negative feedback for controlling the internal voltage VINTto follow to the reference voltage VREF.

If the internal circuit 21 such as the DRAM or the pseudo-SRAM is in theinactive state free of any refresh or any access, then the internalcircuit 21 consumes such a slight current as a leakage of current fromthe device. If an activating signal pulse is inputted into the internalcircuit 21 and the internal circuit 21 is activated, then an internalcurrent of the internal circuit 21 is increased, while the internalvoltage VINT is decreased. The PMOS transistor 23 is transitioned to theON-state by the above-described negative feedback function of theinternal voltage down circuit, thereby increasing the current from theexternal power voltage VDD, whereby the internal voltage VINT isincreased up to the reference voltage VREF.

A timing cycle generation circuit 20 has either one of theconfigurations shown in FIGS. 5 and 8. The timer output TO is inputtedinto the gate electrode of the current source NMOS transistor 24 in thedifferential amplifier 22. The differential amplifier 22 is controlledin operation and non-operation by the timer output TO outputted from thetiming cycle generation circuit 20.

FIG. 11 is a timing chart illustrative of an operation of the timingcycle generation circuit shown in FIG. 8 applied to the internal voltagedown circuit shown in FIG. 10 in accordance with the second embodiment.Operations of the present embodiment will hereinafter be described withreference to FIGS. 10 and 11. FIG. 11 shows the operations in case thatthe circuit shown in FIG. 8 of the second embodiment is used for thetiming cycle generation circuit 20. Notwithstanding, the circuit shownin FIG. 5 of the first embodiment is also applicable to perform the sameoperations. Operations of the timing cycle generation circuit 20 areidentical with the operations shown in FIG. 7 or 9, for which reason thedescriptions in details will be omitted.

In the deep stand-by mode, a power supply is made to only the circuitwhich needs the power supply, while a power for the timing cyclegeneration circuit 20 and the differential amplifier 22 remainsOFF-state, so as not to ensure data hold in the memory cell in theinternal circuit 21.

When this deep-stand-by mode is transitioned to the stand-by mode, thena power supply is made to the timing cycle generation circuit 20 and thedifferential amplifier 22, whereby the operation mode selecting signalMODE becomes “H” (high level). Immediately after the deep stand-by modeis transitioned into the stand-by mode, then the timer signal TR of thesecond cycle shorter than the self-refresh cycle is outputted from thesecond timer circuit and then the timer signal TR is selected andsupplied to the gate electrode of the current source NMOS transistor 24of the differential amplifier 22. The differential amplifier 22 performsa comparative operation of the internal voltage VINT to the referencevoltage VREF every time the timer signal TR of the second cycle isinputted, whereby the internal voltage VINT is made closer to thereference voltage VREF at a high speed.

Thereafter, the chip select signal CS is transitioned to “H” (highlevel) for entry into the active mode from the stand-by mode, so thatthe timing cycle generation circuit 20 outputs the timer signal TN ofthe first cycle which needs the self-refresh. The differential amplifier22 compares the internal voltage VINT to the reference voltage VREF tomake the internal voltage VINT follow to the reference voltage VREF.Independent from the transition between the stand-by mode and the activemode, the timing cycle generation circuit 20 outputs the timer signal TNof the first cycle which needs the self-refresh to make the internalvoltage VINT follow to the reference voltage VREF.

If the internal circuit 21 is inactivated in the stand-by mode, then theinternal circuit 21 consumes such a slight current as a leakage ofcurrent and the internal voltage VINT has a small drop. The timing cyclegeneration circuit 20 of the present invention is applied to the voltagecomparison operation of the differential amplifier 22, so that thedifferential amplifier 22 is inactivated at an interval between pulsesof the timer signal TN of the first cycle synchronizing with the refreshand having been outputted from the first timer circuit 12. At theinterval, the differential amplifier 22 is disconnected from theexternal power voltage VDD for reducing the consumption of current. Inthe transition from the deep stand-by mode to the stand-by mode, it ispossible to improve the high speed performances of boosting the internalvoltage and of transition to the stand-by mode.

In accordance with this embodiment, the above descriptions have beenmade to the operations in transition from the deep stand-by mode to thestand-by mode. Notwithstanding, the timing cycle generation circuit ofthe present invention is applicable to the operation of boosting theinternal; voltage upon power ON to a device incorporating the internalcircuit 21 such as the pseudo-SRAM. In this case, the power-ON signal isused instead of the operation mode selecting signal MODE.

FIG. 12 is block diagram illustrative of an embodiment, wherein thetiming cycle generation circuit according to the present invention isapplied to a substrate back bias generation circuit for supplying a backbias lower than a ground level to a semiconductor substrate.

A substrate back bias generation circuit 30 uses the external powervoltage VDD and the ground level and is operated by the timer output TOfrom the timing cycle generation circuit 20 for generating an internalreference voltage which comprises a back bias voltage VBBG which islower than GND, for example, −1V. An output of the substrate back biasgeneration circuit 30 is connected to a region which needs applicationof the back bias voltage VBBG, for example, to a semiconductorsubstrate, so that the semiconductor substrate has the back bias voltageVBBG which is lower than ground level.

FIG. 13 is a circuit diagram illustrative of a typical example of theback bias generation circuit shown in FIG. 12. As shown in FIG. 13, theabove-described back bias generation circuit 30 comprises a transfertransistor 31 which comprises a PMOS transistor, two pre-chargetransistors 32 and 33, a control logic block 36 receiving an input ofthe timing output TO from the above-described timing cycle generationcircuit 20, a first output driver circuit 34 being controlled by thecontrol logic block 36 for outputting, from its output terminal PI,either one of the external power voltage VDD and the ground level (GND),a second output driver circuit 35 being controlled by the control logicblock 36 for outputting, from its output terminal P2, either one of alower voltage VBB than the external power voltage VDD and the groundlevel (GND), a first capacitance C1 connected between the outputterminal PI of the first output driver circuit 34 and a first node N1between a gate electrode of the transfer transistor 31 and a drainelectrode of the pre-charge transistor 32, and a second capacitance C2connected between the output terminal P2 of the second output drivercircuit 35 and a second node N2 between a source electrode of thetransfer transistor 31 and a drain electrode of the pre-chargetransistor 33.

A capacitance C3 is a capacitance of the semiconductor substrate appliedwith the back bias voltage VBBG. The control logic block 36 receives aninput of the timer output TO from the timing cycle generation circuit 20and controls the pre-charge transistors 32 and 33 and the first andsecond output driver circuits 34 and 35.

FIG. 14 is a timing chart showing a summary of operations of the backbias generation circuit shown in FIG. 13. Operations will be describedwith reference to FIGS. 13 and 14. FIG. 14 shows the operations in casethat the circuit shown in FIG. 8 of the second embodiment is used forthe timing cycle generation circuit 20. Notwithstanding, the circuitshown in FIG. 5 of the first embodiment is also applicable to performthe same operations. Operations of the timing cycle generation circuit20 are identical with the operations shown in FIG. 7 or 9, for whichreason the descriptions in details will be omitted.

In the deep stand-by mode, a power supply is made to only the circuitwhich needs the power supply, while a power for the timing cyclegeneration circuit 20 and the back bias generation circuit 30 remainsOFF-state, and the back bias voltage VBBG is almost identical with theground potential.

When this state is transitioned to the stand-by mode, then a powersupply is made to the timing cycle generation circuit 20 and the backbias generation circuit 30, whereby the operation mode selecting signalMODE becomes “H” (high level). Immediately after the deep stand-by modeis transitioned into the stand-by mode, then the timer signal TR of thesecond cycle shorter than the self-refresh cycle is outputted from thesecond timer circuit 14 and then the timer signal TR is selected andsupplied to the control logic block 36 of the back bias generationcircuit 30. The control logic block 36 performs the following controlsto the transfer transistor 31, the pre-charge transistors 32 and 33 andthe first and second output driver circuits 34 and 35 every time thetimer signal TR of the second cycle is inputted.

Respective output voltages appearing on the output terminals P1 and P2of the first and second output driver circuits 34 and 35 become VDD andVBB (VDD>VBB) respectively, as well as the pre-charge transistors 32 and33 turn ON to charge up the first and second capacitances C1 and C2 atVDD and VBB respectively. Respective output voltages appearing on theoutput terminals P1 and P2 of the first and second output drivercircuits 34 and 35 become the ground potential, as well as thepre-charge transistors 32 and 33 turn OFF, whereby the first node N1becomes −VDD and the second node N2 becomes −VBB by the first and secondcapacitances C1 and C2 charged up at the voltages VDD and VBB,respectively.

Since −VDD<−VBB, the transfer transistor 31 turns ON, the voltage of−VBB, at which the capacitance C2 has been charged up, is transferredthrough the transfer transistor 31 to the substrate capacitance C3. As aresult, the substrate capacitance C3 is charged at a minus potential,whereby the back bias voltage VBBG is dropped to a minus potential. Theabove-described operations will be repeated every time the timing pulseTR from the timing cycle generation circuit 20 is inputted, therebymaking the back bias voltage VBBG follow to the constant voltage of −VBBat a high speed.

Thereafter, the chip select signal CS is transitioned to “H” (highlevel) for entry into the active mode from the stand-by mode, so thatthe timing cycle generation circuit 20 outputs the timer signal TN ofthe first cycle which needs the self-refresh, and supplies the timersignal TN to the back bias generation circuit 30. In the back biasgeneration circuit 30, the voltage of −VBB, at which the capacitance C2has been charged up, is transferred through the transfer transistor 31to the substrate capacitance C3 every time the timing pulse TR isinputted, thereby maintaining the back bias voltage VBBG at the constantvoltage of −VBB.

Independent from the transition between the stand-by mode and the activemode, the timing cycle generation circuit 20 outputs the timer signal TNof the first cycle which needs the self-refresh for maintaining the backbias voltage VBBG at the constant voltage of −VBB.

In accordance with the present embodiment, the substrate capacitance C3is charged up at −VBB every interval between pulses of the timer signalTN of the first cycle outputted from the first timer circuit 12, whereinthe timer signal TN synchronizes with the refresh in the timing cyclegeneration circuit 20 for reducing the consumption of current. In thetransition from the deep stand-by mode to the stand-by mode, it ispossible to improve the high speed performances of boosting the backbias voltage and of transition to the stand-by mode.

In accordance with this embodiment, the above descriptions have beenmade to the operations in transition from the deep stand-by mode to thestand-by mode. Notwithstanding, the timing cycle generation circuit ofthe present invention is applicable to the operation of rising the backbias voltage upon power ON to a device incorporating the pseudo-SRAM. Inthis case, the power-ON signal is used instead of the operation modeselecting signal MODE.

In each of the foregoing embodiments, the above descriptions have beenmade to the operations in case that the deep stand-by mode and thestand-by mode are set as the operation modes of the semiconductor memorydevice. Notwithstanding, the present invention is effectivelyapplicable, in case that the deep stand-by mode not ensuring the datahold of the memory cells is further sub-divided to an operation mode ofdiscontinuing a power supply but only to the refresh control circuitneeded for the refresh and another operation mode of discontinuing anypower supplies to the refresh control circuit, the boost voltagegeneration circuit and the substrate voltage generation circuit, whereinthe invention is applied to the voltage boosting operation in atransition between the sub-divided operation modes.

The above-described stand-by mode and deep stand-by mode are effectiveto suppress the consumption of power. For example, the semiconductormemory device having the above-described stand-by mode and deep stand-bymode is effectively applicable to portable electronic devices.Accordingly, the above-described timing cycle generation circuit iseffectively applicable to semiconductor memory devices integrated inportable electronic devices.

Industrial Applicability:

The present invention provides the following effects.

In accordance with the present embodiment, at the time either of thetransition from the deep stand-by mode to the stand-by mode or of thepower ON, the high speed voltage boosting operation up to such a voltagelevel as enabling refresh operation is executed by the timer cycleshorter than the timer cycle used for cyclically supplying the refreshvoltage to the memory in the stand-by mode, thereby shortening thetransition time from either the deep stand-by mode or the power-ON tothe stand-by mode.

It is also possible to allow the transition to the stand-by mode withinthe above-described time as set if an increase in capacity of the memoryof the device is needed, wherein the device has the stand-by modeensuring the data hold of the memory cells and the deep stand-by mode ofnot ensuring the data hold of the memory cells, and the transition timehas previously been set from either the deep stand-by mode or the powerON to the stand-by mode.

The above-described stand-by mode and deep stand-by mode are effectiveto suppress the consumption of power. For example, the semiconductormemory device having the above-described stand-by mode and deep stand-bymode is effectively applicable to portable electronic devices.Accordingly, the above-described timing cycle generation circuit iseffectively applicable to semiconductor memory devices integrated inportable electronic devices.

1-2. (Cancelled)
 3. A semiconductor memory device having a plurality ofoperation modes, including: a first cycle generation circuit forgenerating timing pulses of a first cycle; a second cycle generationcircuit for generating timing pulses of a second cycle which is shorterthan said first cycle; an internal voltage generation circuit forgenerating a predetermined internal voltage upon receiving inputs ofsaid timing pulses from said first or second cycle generation circuit; atiming pulse switching circuit for selecting said timing pulses fromsaid second cycle generation circuit and supplying said selected timingpulses to said internal voltage generation circuit when saidsemiconductor memory device is transitioned from a first operation modeto a second operation mode in said plurality of operation modes; and acontrol circuit for outputting first, second and third control signalsin accordance with an operation mode selecting signal which selects asingle operation mode in said plurality of operation modes, wherein saidfirst and second cycle generation circuits are controlled in operationand non-operation independently in accordance with said first and secondcontrol signals, respectively, wherein said timing pulse switchingcircuit selects said timing pulses of either one of said first andsecond cycle generation circuits in accordance with said third controlsignal, and wherein said control circuit includes a counter circuit forcounting said timing pulses outputted from said second cycle generationcircuit, and outputting said third control signal when a counted valuebecomes a previously set value.
 4. (Cancelled)
 5. A semiconductor devicehaving a plurality of operation modes, including: a first cyclegeneration circuit for generating timing pulses of a first cycle; asecond cycle generation circuit for generating timing pulses of a secondcycle which is shorter than said first cycle; an internal voltagegeneration circuit for generating a predetermined internal voltage uponreceiving inputs of said timing pulses from said first or second cyclegeneration circuit; and a timing pulse switching circuit for selectingsaid timing pulses from said second cycle generation circuit andsupplying said selected timing pulses to said internal voltagegeneration circuit when said semiconductor memory device is transitionedfrom a first operation mode to a second operation mode in said pluralityof operation modes, wherein said first operation mode is an operationmode of discontinuing a power supply to a predetermined circuit of saidsemiconductor memory device. and said second operation mode is anoperation mode of supplying a power to said predetermined circuit, andwherein said predetermined circuit comprises a circuit necessary forrefresh of memory cells of said semiconductor memory device. 6-12.(Cancelled)
 13. A semiconductor memory device having a plurality ofmemory cells, and having a stand-by mode of supplying a power to acircuit necessary for refreshing memory cells so as to ensure data holdstored in said memory cells, and a deep stand-by mode of discontinuing apower supply to said circuit necessary for refreshing memory cells so asnot to ensure data hold stored in said memory cells, wherein saidsemiconductor memory device includes: an internal voltage generationcircuit being so operated as synchronizing with a refresh cycle forgenerating a predetermined internal voltage; and a timing cyclegeneration circuit for controlling an operation cycle of said internalvoltage generation circuit, and wherein said timing cycle generationcircuit includes: a first timer circuit for setting so that saidoperation cycle of said internal voltage generation circuit synchronizeswith said refresh cycle in said stand-by mode; and a second timercircuit operated in a transition from said deep stand-buy mode to saidstand-by mode for setting so that said operation cycle of said internalvoltage generation circuit is a cycle shorter than said refresh cycle,for making said internal voltage into a predetermined voltage level at ashort time.
 14. The semiconductor memory device as claimed in claim 13,wherein said timing cycle generation circuit further includes: anOR-gate receiving an input of an operation mode selecting signal forswitching said deep stand-by mode and said stand-by mode and alsoanother input of a chip select signal; said first timer circuit beingoperated, when said OR-gate receives an input of either said operationmode selecting signal or said chip select signal, so that said firsttimer circuit outputs a timer signal synchronizing with said refreshcycle; a logic circuit receiving both said operation mode selectingsignal and an output from a one-shot pulse generation circuit, and saidlogic circuit outputting a first level signal when said operation modeselecting signal is transitioned from said deep stand-by mode into saidstand-by mode, and said logic circuit outputting a second level signalupon receipt of said output from said one-shot pulse generation circuit;said second timer circuit being operated, when said logic circuitoutputs said first level signal, so that said second timer circuitoutputs a timer signal with a shorter cycle than said refresh cycle; acounter circuit being re-set by a rising edge, to said first level, ofsaid output from said logic circuit for counting a timer signaloutputted from said second timer circuit, and said counter circuitoutputting a timer output switching signal when a counted value reachesa previously set value; a selecting circuit receiving said timer outputswitching signal from said counter circuit, and said selecting circuitselecting either one of said timer signals from said first and secondtimer circuits for outputting selected one as a timer signal; and saidone-shot pulse generation circuit receiving said timer output switchingsignal from said counter circuit, and said one-shot pulse generationcircuit supplying one-shot pulse to said logic circuit.
 15. Thesemiconductor memory device as claimed in claim 13, wherein said timingcycle generation circuit further includes: an OR-gate receiving an inputof an operation mode selecting signal for switching said deep stand-bymode and said stand-by mode and also another input of a chip selectsignal; said first timer circuit being operated, when said OR-gatereceives an input of either said stand-by mode signal or said chipselect signal, so that said first timer circuit outputs a timer signalsynchronizing with said refresh cycle; a logic circuit receiving bothsaid operation mode selecting signal and said chip select signal, andsaid logic circuit outputting a first logic level signal when saidoperation mode selecting signal is transitioned from said deep stand-bymode into said stand-by mode, and said logic circuit outputting a secondlogic level signal upon receipt of said chip select signal; said secondtimer circuit being operated, when said logic circuit outputs said firstlogic level signal, so that said second timer circuit outputs a timersignal with a shorter cycle than said refresh cycle; and a selectingcircuit for selecting and outputting either one of said timer signalsfrom said first and second timer circuits in accordance with an outputlevel from said logic circuit.
 16. The semiconductor memory device asclaimed in claim 13, wherein said internal voltage generation circuitcomprises a boost voltage generation circuit for generating a boostvoltage to be applied to word lines of memory cells of saidsemiconductor memory device.
 17. The semiconductor memory device asclaimed in claim 13, wherein said internal voltage generation circuitcomprises an internal voltage down circuit for dropping an externalpower voltage and supplies the dropped power voltage to an internalcircuit.
 18. The semiconductor memory device as claimed in claim 13,wherein said internal voltage generation circuit comprises a substrateback bias generation circuit for supplying a semiconductor substratewith a back bias voltage lower than a ground level.
 19. Thesemiconductor memory device as claimed in claim 13, wherein saidsemiconductor memory device comprises a pseudo-SRAM.
 20. A portableelectronic device provided with a semiconductor memory device as claimedin claim
 13. 21. A semiconductor memory device having a plurality ofmemory cells, and having a stand-by mode of supplying a power to acircuit necessary for refreshing memory cells so as to ensure data holdstored in said memory cells, wherein said semiconductor memory deviceincludes: an internal voltage generation circuit being so operated assynchronizing with a refresh cycle for generating a predeterminedinternal voltage; and a timing cycle generation circuit for controllingan operation cycle of said internal voltage generation circuit, andwherein said timing cycle generation circuit further includes: a firsttimer circuit for setting so that said operation cycle of said internalvoltage generation circuit synchronizes with said refresh cycle in saidstand-by mode; and a second timer circuit operated in a transition froma power OFF state to a power ON state for setting so that said operationcycle of said internal voltage generation circuit is a cycle shorterthan said refresh cycle, for making said internal voltage into apredetermined voltage level at a short time.
 22. The semiconductormemory device as claimed in claim 21, wherein said timing cyclegeneration circuit further includes: an OR-gate receiving an input of apower ON signal and another input of a chip select signal; said firsttimer circuit being operated, when said OR-gate receives said power ONsignal and said chip select signal, so that said first timer circuitoutputs a timer signal synchronizing with said refresh cycle; a logiccircuit receiving both said power ON signal and an output from aone-shot pulse generation circuit; said second timer circuit beingoperated, when said logic circuit outputs said first level signal, sothat said second timer circuit outputs a timer signal with a shortercycle than said refresh cycle; a counter circuit being re-set by atransition signal which represents that said output from said logiccircuit is transitioned to said first logic level for counting a timersignal outputted from said second timer circuit, and said countercircuit outputting a timer output switching signal when a counted valuereaches a previously set value; a selecting circuit receiving said timeroutput switching signal from said counter circuit, and said selectingcircuit selecting either one of said timer signals from said first andsecond timer circuits for outputting selected one as a timer signal; andsaid one-shot pulse generation circuit receiving said timer outputswitching signal from said counter circuit, and said one-shot pulsegeneration circuit supplying one-shot pulse to said logic circuit. 23.The semiconductor memory device as claimed in claim 21, wherein saidtiming cycle generation circuit further includes: an OR-gate receivingan input of a power ON signal and another input of a chip select signal;said first timer circuit being operated, when said OR-gate receives saidpower ON signal and said chip select signal, so that said first timercircuit outputs a timer signal synchronizing with said refresh cycle; alogic circuit outputting a first logic level signal upon receipt of saidpower ON signal, and said logic circuit outputting a second logic levelsignal upon receipt of said chip select signal; said second timercircuit being operated, when said logic circuit outputs said first logiclevel signal, so that said second timer circuit outputs a timer signalwith a shorter cycle than said refresh cycle; and a selecting circuitfor selecting and outputting either one of said timer signals from saidfirst and second timer circuits in accordance with an output level fromsaid logic circuit.
 24. The semiconductor memory device as claimed inclaim 21, wherein said internal voltage generation circuit comprises aboost voltage generation circuit for generating a boost voltage to beapplied to word lines of memory cells of said semiconductor memorydevice.
 25. The semiconductor memory device as claimed in claim 21,wherein said internal voltage generation circuit comprises an internalvoltage down circuit for dropping an external power voltage and suppliesthe dropped power voltage to an internal circuit.
 26. The semiconductormemory device as claimed in claim 21, wherein said internal voltagegeneration circuit comprises a substrate back bias generation circuitfor supplying a semiconductor substrate with a back bias voltage lowerthan a ground level.
 27. The semiconductor memory device as claimed inclaim 21, wherein said semiconductor memory device comprises apseudo-SRAM.
 28. A portable electronic device provided with asemiconductor memory device as claimed in claim 21.